|
CS8416的jitter还可以进一步降低,利用Higher Update Rate Phase Detector特性。
PDUR – Changes the type of phase detector used to lock to the active RXP[7:0] input. This bit should only
be set if the sample rate range is between 32 kHz and 108 kHz. If the sample rate is outside of this range
and the PDUR bit is set, loss of lock may occur.
Default = ‘0’
0 – Normal Update Rate Phase Detector - Recovered master clock (RMCK) will have low wideband jitter,
but increased in-band jitter.
1 – Higher Update Rate Phase Detector - Recovered master clock (RMCK) will have low in-band jitter, but
increased wideband jitter. Use this setting for the best performance when the output is connected to a deltasigma
digital-to-analog converter (DAC). |
|